ASIC Synthesis & PPA Engineer

Company description:

Ericsson AB

Job description: Join our Team

About this opportunity:

Do you enjoy solving the hardest problems at the intersection of RTL, timing, power, area and physical implementation? This is an opportunity to take ownership and constraint development for high-performance, low power SoC designs. 

We are hiring an experienced ASIC Synthesis & PPA Engineer.  Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, STA & QoR closure - while also actively identifying opportunities in RTL & microarchitecture level to improve the design PPA.  You will work closely with RTL design, Integration, architecture, place-and-route, and DFT teams throughout the full design cycle.  

What you will do:

• Execute physical-aware and floorplan-driven synthesis flows to reduce post-layout timing and congestion risks.
• Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming. 
• Drive QoR closure by tracking key metrics across design iterations and process corners while providing expert feedback on RTL coding guidelines and synthesizability.
• Work on PPA optimization and structured design space exploration.
• Run block-level and full-chip STA for timing analysis across PVT corners, support MMMC timing closure, and analyze clock domain crossing (CDC) checks.
• Validate UPF/CPF power intent implementation, including isolation cells, level shifters, and retention registers, for correctness and power impact.
• Collaborate with RTL, physical design, and silicon teams on early floorplan exploration, area optimization, pin assignment, and PPA trade-off analysis.
• Apply approved AI-assisted tools for log analysis, QoR comparison, and root cause investigation, while independently validating all generated results with sound engineering judgement. 

The skills you bring:

• 8+ years of experience in physical synthesis or logic design implementation.
• Expert-level experience with Synopsys/Cadence EDA tools.
• Strong SDC constraints authoring and management skills, including clock definitions, generated clocks, I/O delays, and timing exceptions such as false paths and multicycle paths.
• Experience in low power design strategies.
• Experience in analyzing PPA results and providing actionable microarchitecture & RTL-level recommendations to improve the same.
• Proficiency in TCL; Python scripting is a strong plus.
• Multiple tape-outs on 7nm or below